1. Field of the Invention
The present invention relates to an electronic parts packaging structure and a method of manufacturing the same. More specifically, the present invention relates to an electronic parts packaging structure in which a semiconductor chip or the like is mounted on a wiring substrate in the state where the semiconductor chip or the like is buried in an insulating film, and to a method of manufacturing the same.
2. Description of the Related Art
The development of the LSI technology as a key technology to implement multimedia devices is proceeding steadily to a higher speed and a larger capacity of the data transmission. According to this, a higher density of the packaging technology as interfaces between the LSI and electronic devices is also proceeding.
Based on demands for further density growth, a semiconductor device in which a plurality of semiconductor chips are three-dimensionally stacked and mounted on a wiring substrate has been developed. To cite an example, each of Patent Literature 1 (Japanese Unexamined Patent Publication No. 2001-177045) and Patent Literature 2 (Japanese Unexamined Patent Publication No. 2000-323645) discloses a semiconductor device having a structure as follows: a plurality of semiconductor chips are three-dimensionally mounted on a wiring substrate in the state where the semiconductor chips are buried in insulating films, and the plurality of semiconductor chips are mutually connected using multilayered wiring patterns or the like formed with the insulating films interposed therebetween.
However, in the above-described Patent Literatures 1 and 2, there is no consideration for the fact that an interlayer insulating film is formed in the state where steps are generated due to the thickness of a semiconductor chip when the interlayer insulating film is formed on the mounted semiconductor chip.
Specifically, if steps are generated in the interlayer insulating film on the semiconductor chip, defocus is apt to occur in photolithography when wiring patterns are formed on the interlayer insulating film. Accordingly, it is difficult to form desired wiring patterns with high precision.
Furthermore, since steps are also generated in the wiring patterns formed on the interlayer insulating film, reliability of bonding may be lowered when a semiconductor chip is flip-chip bonded to the wiring patterns.